In recent years, with the increased density, scale, and driving speed of large-scale integrated (LSI) circuits, power consumption has also increased. Consequently, problems of reduced performance and shorter life expectancy due to heat generated by the LSI circuits have resulted. To solve such problems, it is necessary to reduce power consumption, for example, by accurately estimating power consumption during the design phase and taking appropriate measures such as circuit modification.
Conventionally, to achieve lower power consumption in LSI circuits, a technique of reducing power consumption by clock gating has been proposed. In clock gating, power consumption is decreased over an entire circuit by stopping the supply of a clock to a module that does not affect operation of the entire circuit.
Further, a design tool has been provided that automatically applies clock gating through operation analysis of the LSI circuit. In addition, Japanese Laid-Open Patent Application Publication No. 2003-330988 discloses a technique of detecting from hardware description, a register constituting a state machine and a register operating only when the state machine is in a non-idle state, and of automatically generating a gated clock supply circuit that supplies a gated clock to the registers.
However, with such a conventional technique employing the use of a design tool to apply clock gating, whether clock gating can be applied is determined through a detailed analysis of the operation of the LSI circuit. Accordingly, there is a problem in that the processing time and analysis load become enormous as circuit scale increases, leading to a prolonged design period.
In addition, according to such a conventional technique of detecting non-idle state states based on hardware description to automatically generate a circuit that supplies a gated clock to registers operating only when a state machine is in a non-idle state, there is a problem in that the burdensome task of checking the specification of the LSI circuit to define the idle states is place on the designer. Further, if a person other than the designer is in charge of reducing power consumption, a greater work load is placed on the person and the time required to achieve reductions in power consumption increases due to the extreme difficulty in defining idle states based on the specification.